There are many advantages to using silicon as a substrate for electronic packaging, rather than traditional ceramic and organic laminate packaging. Key features of the silicon carrier include: the ability to create high performance wiring and joining at much finer pitch than typical packaging, the ability to join heterogeneous technologies or different generation technologies for high speed applications, the ability to integrate passives, MEMs (micro electromechanical systems) or optical fibers, the ability to add silicon functionality to the carrier package in addition to wiring, the ability to dramatically increase the I/O density, and for many applications, the ability to reduce overall system cost when compared to other system on package (SOP) approaches which do not use Si as the carrier.
Elements and structures of semiconductor packages have been described in U.S. Pat. No. 5,998,292 to Black et al. and U.S. Pat. No. 6,593,644 to Chiu et al. The through-via structures described in these two cited works are constructed using a “vias first” process approach described below. In this method, deep blind vias (which may be up to several hundred micrometers in depth) are first etched into a silicon wafer, after which side wall insulation is deposited or thermally grown. The vias are then completely filled with a conductor, after which standard BEOL wiring levels are built on top of the silicon wafer. Up to this point in the process, the vias are still blind. They are converted to through-vias only when the whole wafer is thinned by backside grinding and/or etching to expose the via conductors on the backside. Once exposed, solder connections, such as C4 solder balls may then be built on the carrier back, and chips may be joined to the front, by any one of a number of conventional techniques, such as flip chip bonding.
The “vias first” process flow has the advantage that the side wall insulation process is fairly straightforward since a variety of techniques are available to ensure complete coverage of the side walls including, in many cases, thermal oxidation. Moreover, since the vias terminate in the silicon itself rather than on an etch stopping layer, there is little chance of side wall variation near the base of the via such as abrupt lateral etching or flaring. A smooth uniform side wall combined with thermal oxidation virtually assures high-yield via to via isolation.
On the other hand, in the “vias first” approach the filling of the through-vias must be absolutely complete, void-free and fully sealed at the top in order for wiring levels to be built on top and effectively connected down through the silicon wafer. Further, the conductive material used to fill the vias must be very well matched in coefficient of thermal expansion (CTE) to the silicon substrate otherwise mechanical deformation can take place during subsequent processing of the wiring levels leading to electrical and/or mechanical failure of the carrier by cracking of the silicon, the insulator or by upward pumping of material from within the via itself.
Another process approach is to build the devices and wiring according to the standard CMOS semiconductor process flow, adding the through-vias at the end of the process by driving them through from the back of the wafer. In this “vias last” approach the same techniques can be used to etch the vias e.g. deep anisotropic reactive ion etching (RIE) from an inductively coupled plasma source. However an important difference exists at the location of the via bottom. In the “vias first” process, the vias remains blind until the wafer is thinned to reveal the insulated conductors, at which time further processing must be done to add contact pads and insulate the back of the wafer. In the “vias last” approach the contact pads are built first on the front side of the wafer underneath the wiring levels, and are effectively uncovered at the back side by means of an etching process. This means that the contact pads, typically insulating layer of silicon oxide or silicon nitride perforated with conductive metal vias, act as etch stops.
This would be of little consequence in the case of perfect etch selectivity between the silicon and the etch stop, as well as perfect side wall passivation integrity at the contact pad to silicon interface. In practice, the etch chemistry available in deep Si RIE can be made very selective to common insulators and many metals used to create the contact pads. However, it is well known that side wall passivation in deep anisotropic etching has a tendency to become compromised at etch stop layers, which causes unintended lateral etching to begin at the foot of the via, resulting in reentrant features ranging from an outward flare to dramatic lateral undercutting. Since via insulation and metallization steps must take place after the via etching process, it is paramount that the via side wall be smooth from top to bottom and preferably vertical (slight positive slope is also acceptable) with no discontinuities or negatively flared regions which would make insulation and metal wall coating difficult or impossible.
Because all the wiring levels have already been built in the “vias last” process flow, the temperature cannot exceed a maximum of about 400 degrees C. which makes thermal oxidation impossible. Thus, low-temperature CVD or PECVD insulation with silicon oxide or nitride materials becomes a practical necessity in this case, and these do not coat reentrant via side walls (those having a negative slope or reverse taper) nearly as well as vertical walls, or walls having a slightly positive slope. Also, in the case where electroplating is to be used to coat the side walls with metallization, common liner and seed materials such as TaN, or metals such as Ta and Cu are typically sputtered into the vias, and once again smooth continuous surfaces without negative flare or undercut at the base are required to ensure complete coverage. A number of methods and structures have been described whereby through vias may be etched through silicon from the back in such a fashion as to land on a pad structure on the active side of the wafer. In U.S. Pat. No. 5,608,264 to S. J. Gaul a “vias first” process is described wherein vias begin as blind vias which are metal lined and completely filled with doped polysilicon, and are later exposed by etching the backside of the wafer. In one embodiment of this work, the polysilicon is later removed by wet KOH etching from the backside to create an open through via terminating on an oxide layer under a pad on the active front side. Such a structure avoids the problem of deep etch undercut at the pad interface since the via fill is entirely removed by highly selective wet etch. However, such a process is not a viable “vias last” process but instead is a time-consuming and potentially very expensive “vias first” process. Time and expense can be very high, especially when via diameter is large since the entire via must be first completely filled with CVD polysilicon in order to build the wiring levels, only to have all the polysilicon removed from the backside in a later etching step. As such, one of the most expensive and time consuming CVD steps turns out to be entirely sacrificial in this case.
U.S. Pat. No. 6,608,371 to Kuashima et al. discloses a true “vias last” process flow wherein the metal contact pads are first formed on the front side of a silicon wafer after which tapered through vias are formed using a laser. The vias are insulated, in the preferred embodiment, using a resin which could be made to fill the entire via, then opened again using a second laser etching step to produce a narrower diameter through hole coincident with the first. The via would then be metallized, where the metal could be applied in the form of a metal paste or solder. This method has a process flow which is more akin to board level packaging rather than silicon CMOS processing. In particular, the processing time and cost of using a laser system to create the through-vias grows in proportion to the number and density of vias required. For high-performance applications where several thousand through vias are required per die, and there are several hundred die per wafer, the raw processing time per wafer could be intolerably high. Further, the process so described specifies ranges for the through via diameter on a 50 μm thick wafer of 60 to 80 μm with the inner diameter of the insulated region ranging from about 30 μm to 40 μm. It is clear that vias of outer diameter of about 20 μm or less are difficult to produce or completely inaccessible to this method, whereas diameters down to 1 μm are feasible using deep anisotropic etching.
A CMOS-compatible “vias last” process having many steps generally comparable to the method described herein, but not having the novel steps and structure of the invention described below, can be found in U.S. Pat. No. 6,569,762 to Kong. In Kong the layer where the deep Si RIE etch lands is a blanket layer. For this reason, a second etch step with an oxide selective chemistry must be used to open this insulator and expose the contacts beneath. As has been well noted in the literature, it is extremely difficult in practice to maintain a vertical side wall at such an interface once all Si has been etched from the via. Recognizing the need for a smooth, continuous vertical side wall at the bottom of the via, U.S. Pat. No. 6,569,762 states explicitly that “maintaining the anisotropy of the etch and removal of any polymer material formed after the etch is important to the forming of holes from the back of the wafer to the front oxide. The etching of the holes is stopped at the front oxide by either a timed etch or by detecting a diminishing Si signal using an optical end point detector.”
Simple timing and/or optical methods, while useful, simply cannot provide for a robust wafer scale process because center to edge variation in RIE etch rate is typically seen in all etch systems, which means that vias at different locations will always see a varying degree of over etch. Moreover, wafer thinning techniques such as backside grinding and spin etching are not perfectly uniform processes, especially when the wafers to be thinned are bonded to handling substrates other than Si wafers (e.g. borofloat glass) since these may have a total thickness variation on the order of 10 μm. The compounding effect of center to edge RIE etch variation and non-uniform starting thickness makes it practically impossible to etch each via to the same degree, and thus some attack of the side wall near the via bottom must be anticipated, when the vias are targeted to be fully etched during the first RIE etch step.